As should be understood by one of ordinary skill in the art, depletion mode field effect transistors are in an “on” state when the gate voltage is equal to the source voltage of the transistor, such that current will flow through the drain source juncture of the transistor. A depletion mode device can be turned “off” when the gate voltage is taken below the source voltage by the threshold voltage when current stops flowing through the drain source junction of the transistor.
Some fabrication technologies are either technically limited or cost limited to fabricating only depletion mode field effect transistors. For example, Gallium Nitride (GaN) is presently one such fabrication technology.
Design of analog integrated circuits in Gallium Nitride (GaN) fabrication technology is beginning to gain traction due to its significant benefits over silicon. Specifically, among other things, GaN fabrication technology benefits include high bandwidth, high temperature operation and high breakdown voltages. This is largely due to the fact that GaN has a higher bandgap voltage than silicon (3.49 eV vs 1.1 eV) and higher critical breakdown field (3 MV/cm vs 0.3 MV/cm). At the same time, the fabrication of GaN circuits on a silicon (Si) substrate has made the technology affordable and applicable for a wider range of applications.
The variety of GaN transistor device choices, however, is limited. While n-type depletion and enhancement mode devices are available, p-type GaN devices are not available as they have poor performance due to fundamental device physics issues. Hence the challenge is to make analog circuits using only n-type depletion and enhancement mode devices.
FIG. 1 schematically shows one prior art elementary analog circuit—a gain block that has of a differential pair 100, 101 driving load devices 105, 106. This block provides a differential signal gain while rejecting common mode signals. Getting the highest differential gain out of this circuit is important for building a wide array of high performance analog circuits.
A differential pair of two transistors 100 and 101 when formed in silicon and operating in enhancement mode, such as that shown in FIG. 1, can be loaded with a wide array of load device choices. One choice uses load resistors 220, 221 and is schematically shown in FIG. 2. This circuit has poor gain because the resistors 220, 221 cannot be made sufficiently large as the resistor has to conduct the DC bias current, thus the resistors need to be small. Ideally this circuit could have a current mirror (made of a current sense 331 and a current source device 332) for the load devices of the differential pair 300, 301 as shown in FIG. 3.
The high output impedance of the current source 332 normally provides good differential gain while the current source can provide the DC bias current as needed. In silicon, p-type transistors 400, 401 typically are easily used to design the current mirror (FIG. 4). Undesirably, this option currently is not available in the GaN fabrication process.